A fully integrated 24 GHz fractional PLL with a low-power synchronized ring oscillator divider

This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL with a new low power prescaler. This circuit is implemented in a 0.25 /spl mu/m SiGe:C process from STMicroelectronics (BiCMOS7RF). The PLL power dissipation is 148 mW and fulfills a 24.8 to 26.8 GHz frequency locking range, while exhibiting a phase noise of -97 dBc/Hz at 100 kHz from the carrier. The simulated PLL unity-gain bandwidth is 27 MHz, with a phase margin of 56 /spl deg/. The PLL uses a new latch-based prescaler (SRO) which exhibits a very low power dissipation of 0.74 GHz/mW.

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