Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL

This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark benchmark score. Unlike previously reported <xref ref-type="bibr" rid="ref1">[1]</xref>, this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only <inline-formula> <tex-math notation="LaTeX">$1881~\mu \text{m}^{2}$ </tex-math></inline-formula> per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.