Pipelined structure based on radix-22 FFT algorithm

This paper presents a single-path pipelined hardware structure for DFT computation based on the radix-22 FFT algorithm. The proposed structure requires log4N −1 complex multipliers, log2N complex adder/subtracters and 2(N −1) complex data stores. Compared with previously reported single-path pipelined structures, the number of add/subtracters is reduced by 50 percents. A realization of the delay and commutation function with RAMs is also presented for minimizing the required chip area and power assumption.

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