Jitter minimization in Digital Transmission using dual phase locked loops

Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. In this paper, a new method for minimization of timing jitter due to phase locked loops is described. The timing jitter can be minimized using two phase locked loops connected in cascade, where the first one has Voltage Controlled crystal Oscillator (VCXO) to eliminate the input jitter and the second is a wide band phase locked loop. Usually, RMS jitter is used to describe jitter performance of the system and that can be analyzed. Simulation results for the measurement of jitter in both phase locked loop using MATLAB Simulink are presented. The methodology described is also applicable to other types of clock generator.

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