Optimal synthesis of control logic from behavioral specifications

This paper presents a method of synthesizing control for synchronous digital circuits starting from a behavioral description of the hardware. The input to the control synthesis task is an abstraction of hardware behavior based on sequencing graphs. The model is a concise way of specifying both control and data dependencies, and support hierarchy, unbounded delay operations such as data-dependent loops and external synchronizations, and multiple threads of concurrent execution flow. We show how the sequencing graph can be mapped directly to a modular interconnection of finite state machines. The approach, called adaptive control, is different from other control schemes in that it takes into account the dynamic variations in the execution delay of operations due to the changing inputs. It is optimal by guaranteeing the minimum number of cycles in the execution of a hardware behavior for all input sequences., Specifically, there are no performance penalties for the arbitrary nesting of procedure calls, conditionals, or loops. The adaptive control model and implementation are used within the framework of the HERCULES/HEBE High-Level Synthesis system.