An approach, Beta, for computing testability is presented. This approach is based on analyzing the circuit's behavior description data flow graph (DFG). First, each path in the DFG is analyzed to find the set of paths to justify and propagate each data register. Then, register classification follows to diagnose every register's controllability and observability and classify them into several groups. For the most controllable and observable registers, Beta, unlike other testability methods which compute only testability, also tries to derive the exact sequence for justifying and propagating each register. Register classification is also useful in pointing out hard-to-control and hard-to-observe areas of the circuit. This approach has been implemented in a computer program and applied to several examples. These results are verified by a DFG-based test generator and proven to be successful.<<ETX>>
[1]
Jacob A. Abraham,et al.
An easily computed functional level testability measure
,
1989,
Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[2]
Alice C. Parker,et al.
The high-level synthesis of digital systems
,
1990,
Proc. IEEE.
[3]
Premachandran R. Menon,et al.
An approach to functional level testability analysis
,
1989,
Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[4]
Jack Edward Stephenson,et al.
A testability measure for register-transfer level digital circuits
,
1974
.
[5]
Sheldon B. Akers,et al.
Binary Decision Diagrams
,
1978,
IEEE Transactions on Computers.
[6]
L. H. Goldstein,et al.
SCOAP: Sandia Controllability/Observability Analysis Program
,
1988,
17th Design Automation Conference.