FPGA-based fault simulator

Fault simulation allows evaluation of reliability properties of developed designs. The complexity of the designs is growing, which makes software-based simulation methods unusable. Hardware-based fault simulation can bring desired speedup. Partial dynamic reconfiguration is a way of fault injection. Reconfiguration time is often considered as a main weakness of this technique. This paper describes an FPGA-based fault simulator, where reconfiguration is performed by an embedded processor core, which eliminates this drawback. Error-detection-code based CED circuits are used in experiments; the results of the experiments are reported

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