Thermal management of a C4/CBGA interconnect technology for a high-performance RISC microprocessor: the Motorola PowerPC 620/sup TM/ microprocessor

This paper presents various thermal management options for a high-performance RISC microprocessor available for controlled-collapse-chip-connection (C4) die attached to a ceramic-ball-grid-array substrate (CBGA), as they apply to air-cooled systems. Computational-fluid dynamics (CFD) methods are used to solve the conjugate heat transfer problems and a thermal test vehicle mounted to a printed-circuit board was used to validate the models. The internal package's contribution is typically less than 18% of the overall junction-to-ambient temperature rise. Of this 18%, approximately 85% is associated with the thermal paste internally sealed; while, the lid and the silicon chip account for the other 15% (approximately equal). For moderate airflow applications in the 1 to 4 m/s, the PowerPC 620 microprocessor will require a relatively large heat sink, approximately 20 times that of the C4/CBGA package, to maintain its die-junction temperature. The proper selection of a thermal interface material is critical in minimizing the thermal contact resistance between the package and the heat sink. Considering, the low interface pressure, the synthetic grease offers the best performance.

[1]  H. I. Rosten.  DELPHI-a status report on the European-funded project for the development of libraries and physical models for an integrated design environment , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

[2]  A. Bar-Cohen,et al.  Theta /sub JC/ characterization of chip packages-justification, limitations, and future , 1989, Fifth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium.

[3]  D. Gerke,et al.  A hi-density C4/CBGA interconnect technology for a CMOS microprocessor , 1994 .

[4]  G. B. Kromann.  Thermal management of a C4/ceramic-ball-grid array: the Motorola PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors , 1996, Twelfth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings.

[5]  David Gerke,et al.  Motorola's PowerPC 603 and PowerPC 604 RISC microprocessor: the C4/ceramic-ball-grid array interconnect technology , 1995, 1995 Proceedings. 45th Electronic Components and Technology Conference.

[6]  G. B. Kromann.  Thermal modeling and experimental characterization of the C4/surface-mount-array interconnect technologies , 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.

[7]  J. A. Andrews,et al.  Package thermal resistance model dependency on equipment design , 1988, Fourth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium.

[8]  K. DeHaven,et al.  Controlled collapse chip connection (C4)-an enabling technology , 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.