Prototype design of cluster-based homogeneous Multiprocessor System-on-Chip

The Multiprocessor System-on-Chip (MPSoC) is a promising solution for future complex computer and embedded systems. And, the Network-on-Chip (NoC) has been proposed as the future on-chip interconnection. Whereas, the NoCs bring more challenge on parallel programming and synchronization of different processor cores. This paper proposes a new cluster-based homogeneous MPSoC architecture, which adopts the hybrid interconnection composed of both bus-based and NoC architecture. This architecture has been implemented as a prototype by FPGA device, which integrates 17 processor cores. The performances of this prototype are evaluated under two real applications, matrix chain multiplication and JPEG picture decoding. The speedup ratio of this prototype is up to 15.850.

[1]  Luca Benini,et al.  HW-SW emulation framework for temperature-aware design in MPSoCs , 2008, TODE.

[2]  John Goodacre,et al.  Parallelism and the ARM instruction set architecture , 2005, Computer.

[3]  Ahmed Amine Jerraya,et al.  Multiprocessor System-on-Chip (MPSoC) Technology , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[5]  Song Yu-Kun,et al.  Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[6]  Henry Hoffmann,et al.  On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.

[7]  Luca Benini,et al.  On-Chip Communication Architectures: System on Chip Interconnect , 2008 .

[8]  Sriram R. Vangal,et al.  A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.

[9]  Ming-Lun Gao,et al.  Design of a Hierarchy-Bus Based MPSoC on FPGA , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[10]  Fabrizio Petrini,et al.  Cell Multiprocessor Communication Network: Built for Speed , 2006, IEEE Micro.