Comparative evaluation of latency reducing and tolerating techniques
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Anoop Gupta | Todd C. Mowry | Wolf-Dietrich Weber | Kourosh Gharachorloo | John L. Hennessy | T. Mowry | J. Hennessy | K. Gharachorloo | W. Weber | Anoop Gupta
[1] David Kroft,et al. Lockup-free instruction fetch/prefetch cache organization , 1998, ISCA '81.
[2] Anant Agarwal,et al. Performance Tradeoffs in Multithreaded Processors , 1992, IEEE Trans. Parallel Distributed Syst..
[3] Anoop Gupta,et al. Tolerating Latency Through Software-Controlled Prefetching in Shared-Memory Multiprocessors , 1991, J. Parallel Distributed Comput..
[4] Anoop Gupta,et al. Performance evaluation of memory consistency models for shared-memory multiprocessors , 1991, ASPLOS IV.
[5] Alexander V. Veidenbaum,et al. Compiler-directed data prefetching in multiprocessors with memory hierarchies , 1990 .
[6] Anoop Gupta,et al. The directory-based cache coherence protocol for the DASH multiprocessor , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[7] Anant Agarwal,et al. APRIL: a processor architecture for multiprocessing , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[8] David E. Culler,et al. Analysis of multithreaded architectures for parallel computing , 1990, SPAA '90.
[9] Anoop Gupta,et al. Memory consistency and event ordering in scalable shared-memory multiprocessors , 1990, ISCA '90.
[10] A. Gupta,et al. Parallel distributed-time logic simulation , 1989, IEEE Design & Test of Computers.
[11] Randy H. Katz,et al. Evaluating The Performance Of Four Snooping Cache Coherency Protocols , 1989, The 16th Annual International Symposium on Computer Architecture.
[12] Anoop Gupta,et al. Exploring The Benefits Of Multiple Hardware Contexts In A Multiprocessor Architecture: Preliminary Results , 1989, The 16th Annual International Symposium on Computer Architecture.
[13] J. Mcdonald,et al. Vectorization of a particle simulation method for hypersonic rarefied flow , 1988 .
[14] Bob Iannucci. Toward a dataflow/von Neumann hybrid architecture , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.
[15] Robert H. Halstead,et al. MASA: a multithreaded processor architecture for parallel symbolic computing , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.
[16] Andrew W. Wilson,et al. Hierarchical cache/bus architecture for shared memory multiprocessors , 1987, ISCA '87.
[17] James H. Patterson,et al. Portable Programs for Parallel Processors , 1987 .
[18] James K. Archibald,et al. Cache coherence protocols: evaluation using a multiprocessor simulation model , 1986, TOCS.
[19] Burton J. Smith. Architecture And Applications Of The HEP Multiprocessor Computer System , 1982, Optics & Photonics.
[20] Leslie Lamport,et al. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.
[21] James R. Goodman,et al. Cache Consistency and Sequential Consistency , 1991 .
[22] Helen Davis,et al. Tango introduction and tutorial , 1990 .
[23] M. Hill,et al. Weak ordering-a new definition , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[24] Ken Kennedy,et al. Software methods for improvement of cache performance on supercomputer applications , 1989 .
[25] Pen-Chung Yew,et al. : Data Prefetching In Shared Memory Multiprocessors , 1987, ICPP.
[26] Pen-Chung Yew,et al. The effectiveness of caches and data prefetch buffers in large-scale shared memory multiprocessors , 1987 .
[27] Kevin P. McAuliffe,et al. The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture , 1985, ICPP.