A 1.8-V 3-MS/s 13-bit /spl Delta//spl Sigma/ A/D converter with pseudo data-weighted-averaging in 0.18-/spl mu/m digital CMOS

A 1.8 V /spl Delta//spl Sigma/ modulator, fabricated in a 0.18 /spl mu/m standard digital CMOS process, achieves 81 dB SFDR and 74 dB SNR over a 3 MS/s conversion bandwidth. Its single-loop single-feedback architecture uses a 3rd-order FIR noise-transfer- function and a 5 bit quantizer to render the quantization noise negligible at 16/spl times/ oversampling. A pseudo data-weighted-averaging technique linearizes the multibit feedback D/A converter, while eliminating the inband signal-dependent tones. The bootstrapped switches in the switched-capacitor implementation reduce the sampling distortion for a 1.85 V/sub pp/ input-signal range. The analog and digital power consumptions are 32.4 mW and 12.6 mW, respectively. The on-chip references dissipate 14.4 mW.