Performance evaluation of four assiciative disk designs

Abstract This paper discusses a model for associative disk architectures. Simulation results of an event driven simulation based on this model are presented. The designs analyzed are Processor-per-Track (PPT), Processor-per-Bubble-cell (PPB), Processor-per-Head (PPH), and Processor-per-Disk (PPD). The effects of a number of factors, including output channel contention, availability of index information, impact of mark-bits, and channel allocation policy on the performance of these machines were tested. It is shown that while in the general case the PPT architecture is best, the performance of the PPB design is remarkably good considering the slow speed of bubble memory chips. Also the availability of index information can be used by both the PPH and PPD architectures to improve their performance to a level almost comparable to PPT.

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