A distributed shared memory multiprocessor ASURA: memory and cache architecture

ASURA is a large scale, cluster-based, distributed, shared memory, multiprocessor being developed at Kyoto University and Kubota Corporation. Up to 128 clusters are interconnected to form an ASURA system of up to 1024 processors. The basic concept of the ASURA design is to take advantage of the hierarchical structure of the system. Implementing this concept, a large shared cache is placed between each cluster and the inter-cluster network. The shared cache and the shared memories distributed among the clusters form part of ASURA's hierarchical memory architecture, providing various unique features to ASURA. In this paper, the hierarchical memory architecture of ASURA and its unique cache coherence scheme, including a proposal of a new hierarchical directory scheme, are described with some simulation results.

[1]  Dhiraj K. Pradhan,et al.  Two economical directory schemes for large-scale cache coherent multiprocessors , 1991, CARN.

[2]  Anoop Gupta,et al.  The directory-based cache coherence protocol for the DASH multiprocessor , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[3]  Vincent A. Guarna,et al.  A Technique for Analyzing Pointer and Structure References In Parallel Restructuring Compilers , 1988, ICPP.

[4]  城和貴,et al.  Performance Evaluation of the ASURA Cluster , 1992 .

[5]  Susan J. Eggers,et al.  Eliminating False Sharing , 1991, ICPP.

[6]  Kevin P. McAuliffe,et al.  RP3 Processor-Memory Element , 1985, ICPP.

[7]  Per Stenström,et al.  A Survey of Cache Coherence Schemes for Multiprocessors , 1990, Computer.

[8]  Anoop Gupta,et al.  Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes , 1990, ICPP.

[9]  Alexander V. Veidenbaum,et al.  The Organization of the Cedar System , 1991, ICPP.

[10]  Creve Maples,et al.  A high-performance, memory-based interconnection system for multicomputer environments , 1990, Proceedings SUPERCOMPUTING '90.

[11]  Anoop Gupta,et al.  The directory-based cache coherence protocol for the DASH multiprocessor , 1990, ISCA '90.

[12]  A. Richard Newton,et al.  An empirical evaluation of two memory-efficient directory methods , 1990, ISCA '90.

[13]  Hendrik A. Goosen,et al.  Paradigm: a highly scalable shared-memory multicomputer architecture , 1991, Computer.

[14]  Mark D. Hill,et al.  Weak ordering- a new definition and some implications , 1989, ISCA 1989.

[15]  Andrew W. Wilson,et al.  Hierarchical cache/bus architecture for shared memory multiprocessors , 1987, ISCA '87.

[16]  Michel Dubois,et al.  Synchronization, coherence, and event ordering in multiprocessors , 1988, Computer.

[17]  Anoop Gupta,et al.  Memory consistency and event ordering in scalable shared-memory multiprocessors , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[18]  James K. Archibald,et al.  An economical solution to the cache coherence problem , 1984, ISCA '84.

[19]  Willy Zwaenepoel,et al.  Toward Large-Scale Shared Memory Multiprocessing , 1992 .

[20]  Ken Kennedy,et al.  Software prefetching , 1991, ASPLOS IV.

[21]  Alexander V. Veidenbaum,et al.  Compiler-directed cache management in multiprocessors , 1990, Computer.

[22]  Alexander V. Veidenbaum,et al.  A software coherence scheme with the assistance of directories , 1991, ICS '91.

[23]  James Archibald,et al.  An economical solution to the cache coherence problem , 1984, ISCA 1984.