CSP BOARD LEVEL RELIABILITY-RESULTS

The fatigue and damage of solder joints of area array components as well as the potential for interface failure within chip scale packages (CSP with flex, rigid respectively ceramic interposer) are primarily caused by thermal loading (ambient and/or operating conditions). The thermally induced residual stresses depend on the CTEmismatch encountered during thermal cycle tests (TCT) and, for power cycle tests (PCT), also on the gradient of the temperature distribution. In order to characterize the potential for failure TCTs and PCTs were used to analyze the board level reliability of different area array components. The reliability is the result of the interaction of different materials and interfaces on component side as well as on board side. For BGAs a lot of fatigue tests are described up to now. Selection guides based on package size, die size, laminate, thickness of interposer, mold thickness, numbers of ball rows, array type etc. are published. The paper outlines CSP package analysis in comparison to BGA types of area array packages. The important point of interest is the applied interposer, the influence of package level interfaces, geometry, package constitution, ball array on the board level reliability. On testand functional boards the electrical continuity was studied under different test conditions. The successful and safe development of increasingly miniaturized microelectronic structures, such as CSP packages, requires a twofold validation process based on package level and board level qualification. Only the combination of both allows to quickly react to the rapid development of new structures and to actively define the process of their future evolution. Within the pre-reflow “package qualification” the warpage analysis is used to describe the strain and stress level in the package and in the occupied pad area on board. With combination of warpage measurements after reflow simulation and detection of the z-displacement of the package after solder solidification, results regarding the permanent deformations are available describing mechanical strain/stress in the package, ball solder joints and board. The z-displacement level (strain / stress) is one of the inputs for interpreting onor offline detected electrical discontinuities. For this reason specially wired boards were used for extended test trials. Studying the board level reliability different board types (conventional, high density laminates; different core materials and μvia-technologies) were used analyzing the assembly quality and the reliability. The kind of board used to assemble CSP on board is a concern. Weibull-plots offer the possibility to compare reliability and lifetime data on BGA side with CSP, depend on board solutions, interconnection quality and aging conditions. Tests done analyzed various CSP geometry’s and materials (flex, rigid and ceramic based interposer). The data for the warpage characteristic of packages, laminates and assemblies as well as the cumulated failure distribution depend on cycles (TCT, PCT) and results of microsections in failed areas/interconnections were used as a basis to generate specific Weibull-plots. INTRODUCTION The paper outlines: CSP Package analysis in comparison to BGA types of area array packages; Influence of interfaces, geometry, package constitution, ball array, interposer, etc.; Characterization of laminates used for advanced packages (conventional and HDI-substrates); Dimensional stability of substrates depend on constitution, thickness, wiring, adhesion properties, physical data, etc.; Characterization of strains and stresses in CSP ball solder joints depend on package type and temperature profiling of the reflow process; Warpage analysis depend on package type and substrates, thermal loading of single CSP, occupied areas on board, reflow simulation; Interconnection quality depend on package constitution; Destructive evaluation examples; Warpage behavior of different CSP packages measured on package side and after reflow process; Ranking discussion depend on package type; Overview about test files, test strategy, readouts, criteria, interrupts and localization of interrupts, influence of substrates; Test files used for reliability studies Methods to characterize the degradation behavior of CSP ball solder joints with exploitation of relevant features concerning the reliability; TherMoire , Rodenstock, contact method z-displacement measurement , microsections; Microsections of interfaces (first and second level); Typical examples characterizing interrupts and/or discontinuities; Nondestructive and destructive measurements to describe limitations of the functional stability on board level – exploitation of detected failures Measurements related to electrical test procedures; Weibull plots (comparison to conventional devices) CSP packages tested were based on (leadframe), flex, rigid and ceramic interposer. The main deviation from direct chip attach is the addition of interposer between the silicon and the next interconnection area to which attachment is made. This interposer serve as compliant, space transformer and mechanical protection. BGAs with BT interposer were used to compare lifetime results CSP vs. BGA after TCT and PCT. Table 1 includes an overview about published CSP-tests and results. From Table 1, it is obvious that each semiconductor supplier has its own test files and conditions depending on application. To compare different packages it seems to be necessary to know more details concerning the board level reliability. Package tested by Test Testcondition No. of Cycles / Hours Failures Literature TCT (brd.) -65°C/150°C 24cpd >500C 0/40 TCT (pkg.) -65°C/150°C 24cpd 500C 0/25 MCSP96 TCT(brd.) 0/20 MCSP96 /w Underfiller TCT(brd.) 0/3 CSP40 (DRAM) Hitachi TCT(brd.) -55°C/125°C 1500C 0/21 CHR97, Chu97 TCT(Ceramic brd.) -65°C/'150°C 1000C 4/78 TCT(FR4 brd.) -55°C/125°C 1000C 0/78 BLP28 I (16Mb DRAM) TCT(brd.) 11/11 TCT(brd. Padvar.1) 5/6 TCT(brd. Padvar.2) 6/6 TCT(brd. Padvar.3) 4/6 CSP48 900C 0/20 CSP160 500C 1/5 CSP180 500C 0/22 -55°C/125°C 5'/5' 1500C 0/6 -65°C/150°C 30'/30' 1500C 0/6 μBGA172 Shinko Corp. TCT(brd. Padvar.1) Abe96 Sharp Corp. TCT(brd.) -40°C/125°C KY+97 BLP28 II (16Mb DRAM) -55°C/125°C (MIL883C Cond.B) YGKS+97 1000C Intel Co. μBGA46 (4Mb FLASH) Gre96, RI97, Chu97 LG Semicon CHR97, Chu97 SON26 (Flash ROM) Fujitsu Mitsubishi -40°C/125°C, 1h 500C CHR97 Table 1 Accelerated Lifetime Test – Published CSP Board Level Reliability Test Data CSP Packages (geometry, package constitution, ball array, interposer) To analyze package constitution driven degradation features the CSP packages listed in Table 2 were used in the lifetime test. The important parameters CSP dimension, interposer & thickness, die dimension, die thickness, first level characterization are presented. The objectives in this paper are as follows: First, it is intended to electrically analyze the board level reliability as well as the first level behavior of differently structured but fully assembled CSP-packages when subjected to thermal cycling between high and low temperature levels (20°C to +100°C; -40°C to +125°C) as well as to power cycle tests. Quantities of interest include thermal stresses and strains which develop in the various layers of the structures, a quantitative assessment of the influence of defects responsible for electrical discontinuities or interrupts, such as debonding or imperfections in the glue, accumulation of irreversible plastic and creep strains in the solder balls, as well as identification of particularly heavily strained regions within the solder. These results will be tested with real structures on board level. Pitch (mm) No. of I/O Package L x B (mm x mm) Chip L x B (mm x mm) Chip Thickn. (μm) CSP-f-1 A PI 50 0,8 180 12x12 10,4x10,4 300 Au-WB yes CSP-f-2 A PI 50 0,8 72 8x8 6,24x6,24 300 Au-WB yes CSP-r-1 A C 400 0,8 160 13x13 9,34x9,55 300 Au-WB no CSP-r-2 A C 400 0,8 22 5x3,8 1,55x1,55 280 C4 no CSP-r-3 A BT 200 0,8 161 13x13 9,34x9,55 300 Au-WB no CSP-f-3 A PI 75 0,75 46 5,7x7,8 5,25x7,4 430 CuAu-lead yes BGA-r-1 A BT 970 1,27 352 35x35 13,23x13,23 330 Au-WB yes + R FC-1 A 0,475 48 6,3x6,3 575 yes FC-2 A 0,203 96 5,6x6,4 575 yes CSP-f-3 B PI 75 0,8 160 12x12 10,4x10,4 300 Au-WB yes CSP-f-4 B PI 75 0,8 160 12x12 10,4x10,4 300 Au-WB yes CSP-f-5 B PI 50 0,8 72 8x8 6,5x6,24 300 Au-WB yes CSP-f-6 B PI 50 0,8 72 8x8 6,5x6,24 300 Au-WB yes CSP-f-7 B PI 50 0,8 160 12x12 9,6x9,1 285 Au-WB no CSP-fr-1 C PICU 80 0,5 216 15x15 8x7,6 375 TAB yes CSP-f-8 C PI 50 0,75 48 8,03x10,42 6,53x8,92 280 CuAu-lead yes CSP-f-1 C PI 50 0,8 180 12x12 10,4x10,4 300 Au-WB yes CSP-r-3 C BT 200 0,8 161 13x13 9,34x9,55 300 Au-WB no CSP-f-9 C PI 37 0,8 48 5,7x7,8 5,25x7,4 430 CuAu-lead yes CSP-r-4 D C 400 0,8 144 11x11 6,7x6,7 300 Au-WB yes CSP-r-3 E BT 275 0,8 160 13,04x13,04 5,3x5,2 280 Au-WB funct. CSP-f-3 E PI 75 0,8 160 12,15x12,15 7,31x6,87 320 Au-WB funct. Package: f-flexible, r-rigid, Interposer: PI-Polyimid, BT-Bismaleimide triazine, C-HTC Ceramic; 1.Level: WB-Wire Bond 1.Level Daisy Chain (DC) Package TB Interposer (Material & Thick. μm) Dimensions Table 2: Overview-CSP Package Data – Board Level Reliability Three different CSP packages were considered which differ in the type of substrate that was used and the number of rows of balls along the perimeter: (a) PI-flex, (b) ceramic, and (c) an BT-resin laminate. Details of the dimensions were specified by the manufacturers and, in addition, micro-graphs of the cross-sections were used to obtain accurate geometry data, in particular for the solder balls after reflow. All CSP tested were microsectioned before testing to know the package constitution and the interfaces responsible for stress accumulation. Details describing the CSP are listed in Table 2. Testboards and Test-Conditions for Board Level Reliability Tests Table 3 shows one of the applied test boards and gives details about materials (conventional, HDI), finishes, NSMD-pads and add