Modelling circuit delays in a demand driven simulator

Abstract Logic-level simulation of a digital circuit is commonly effected using a discrete event-driven strategy. We have, alternatively, employed a demand-driven simulation strategy in which simulation speed is improved by avoiding unnecessary component activations and signal evaluations. In this paper we describe the application of this method to the simulation of both logic and timing behaviour. Preliminary results are presented, showing significant performance gains in comparison with event-driven simulation.

[1]  T. C. Raymond,et al.  Tutorial Series 10 LSI/VLSI Design Automation , 1981, Computer.

[2]  S. G. Chappell,et al.  Lamp: Logic-circuit simulators , 1974 .

[3]  Donald E. Thomas,et al.  Defining and Implementing a Multilevel Design Representation with Simulation Applications , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  M. Ray Mercer,et al.  Demand Driven Simulation: BACKSIM , 1987, 24th ACM/IEEE Design Automation Conference.

[5]  Stephen A. Szygenda,et al.  Digital Logic Simulation in a Time-Based, Table-Driven Environment , 1975, Computer.

[6]  Peter Henderson,et al.  A lazy evaluator , 1976, POPL.

[7]  Dwight D. Hill,et al.  SABLE: A Tool for Generating Structured, Multi-Level Simulations , 1979, 16th Design Automation Conference.

[8]  Randal E. Bryant.  MOSSIM: A Switch-Level Simulator for MOS LSI , 1981, 18th Design Automation Conference.

[9]  A. Richard Newton,et al.  Electrical-logic simulation and its applications , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Ernst G. Ulrich.  Exclusive simulation of activity in digital networks , 1969, CACM.