Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications

This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The software developed for IP image compression achieves high quality ratios over classic methodologies by exploiting the inherent redundancy that is present in IP images. However, there are certain time constraints to the software approach that must be confronted in order to address real-time applications. Our main effort is to achieve real-time performance by implementing in hardware the most time-consuming parts of the compression algorithm. The proposed novel digital architecture features minimized memory read operations and extensive simultaneous processing, while taking into concern the memory and data bandwidth limitations of a single FPGA implementation. Our results demonstrate that the implemented hardware system can successfully process high resolution IP video sequences in real-time, addressing a vast range of applications, from mobile systems to demanding desktop displays.

[1]  Roger F. Woods,et al.  VLSI architectures for field programmable gate arrays: a case study , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[2]  A. Bourgougnon.  Comptes Rendus de l'Académie des Sciences. , 1879 .

[3]  Keikichi Tamaru,et al.  A memory efficient array architecture for real-time motion estimation , 1998, Systems and Computers in Japan.

[4]  Nuno Roma,et al.  Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs , 2003, FPL.

[5]  Ville Kyrki.  Jbig Image Compression Standard , 1999 .

[6]  Stephan Wong,et al.  Alternatives in FPGA-based SAD implementations , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[7]  N. P. Sgouros,et al.  Compression of IP images for autostereoscopic 3D imaging applications , 2003, 3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the.

[8]  Gert Slavenburg,et al.  An architectural overview of the programmable multimedia processor, TM-1 , 1996, COMPCON '96. Technologies for the Information Superhighway Digest of Papers.

[10]  Hongen Liao,et al.  Intra-operative Real-Time 3-D Information Display System Based on Integral Videography , 2001, MICCAI.

[11]  Stamatis Vassiliadis,et al.  A sum of absolute differences implementation in FPGA hardware , 2002, Proceedings. 28th Euromicro Conference.

[12]  P. Harman,et al.  Home based 3D entertainment-an overview , 2000, Proceedings 2000 International Conference on Image Processing (Cat. No.00CH37101).

[13]  N. Theofanous,et al.  An Area-Efficient FPGA Implementation of a Disparity Estimation Scheme for Real-Time Compression of IP Images * , 2004 .

[14]  Maurizio Martina,et al.  Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming , 2002, Proceedings. IEEE International Conference on Multimedia and Expo.

[15]  M. Halle.  Autostereoscopic displays and computer graphics , 1997, COMG.

[16]  Janusz Konrad,et al.  Visual communications of tomorrow: natural, efficient, and flexible , 2001, IEEE Commun. Mag..

[17]  S. Ramachandran,et al.  FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression , 2001, FPGA '01.

[18]  Jens-Rainer Ohm,et al.  A realtime hardware system for stereoscopic videoconferencing with viewpoint adaptation , 1998, Signal Process. Image Commun..

[19]  Amar Aggoun,et al.  Adaptive 3D-DCT compression algorithm for continuous parallax 3D integral imaging , 2002, Signal Process. Image Commun..