Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

Bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD) degrade the performance of circuits, such as FinFET-based SRAMs. In this paper, a unified modeling methodology is applied for SRAM reliability degradation due to BTI and HCI, which are implemented with a time-dependent threshold voltage model, and GOBD which is implemented with a comprehensive current model. The applicability of degradation models is verified through fitting and comparison with the measured results. SRAM cell lifetime due to different mechanisms is calculated with Monte Carlo simulations to determine the performance degradation. The combined lifetime distribution and failure probability of an SRAM is further analyzed while considering the effect of Error Correcting Codes (ECC). Based on the different degrees of sensitivity, the potential of designing optimal accelerated life tests due to different failure mechanisms is discussed.

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