Reliability Management through Testing.

Abstract : This final report mentions the research results of this project. They are grouped into technology - specific testing, IPPQ Testing, fault modeling and testing of storage elements and arrays and reliability growth for design faults.

[1]  James M. Bieman,et al.  The relationship between test coverage and reliability , 1994, Proceedings of 1994 IEEE International Symposium on Software Reliability Engineering.

[2]  Yashwant K. Malaiya,et al.  The scaling problem in neural networks for software reliability prediction , 1992, [1992] Proceedings Third International Symposium on Software Reliability Engineering.

[3]  Pradip K. Srimani,et al.  On the need for simulation for better characterization of software reliability , 1993, Proceedings of 1993 IEEE International Symposium on Software Reliability Engineering.

[4]  Anura P. Jayasumana,et al.  A novel high-speed BiCMOS domino logic family , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[5]  S. M. Menon,et al.  Testable design of BiCMOS circuits for stuck-open fault detection using single patterns , 1995, IEEE J. Solid State Circuits.

[6]  Yashwant K. Malaiya,et al.  Neural networks for software reliability engineering , 1996 .

[7]  Pradip K. Srimani,et al.  An Examination of Fault Exposure Ratio , 1993, IEEE Trans. Software Eng..

[8]  L. Darrell Whitley,et al.  Prediction of Software Reliability Using Connectionist Models , 1992, IEEE Trans. Software Eng..

[9]  Anura P. Jayasumana,et al.  The effect of built-in current sensors (BICS) on operational and test performance /spl lsqb/CMOS ICs/spl rsqb/ , 1994, Proceedings of 7th International Conference on VLSI Design.

[10]  S. M. Menon,et al.  Modeling of faulty behavior of ECL storage elements , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.

[11]  Anura P. Jayasumana,et al.  Faulty behavior of asynchronous storage elements , 1993 .

[12]  Pradip K. Srimani,et al.  The nature of fault exposure ratio , 1992, [1992] Proceedings Third International Symposium on Software Reliability Engineering.

[13]  Yashwant K. Malaiya,et al.  Detection of feed-through faults in CMOS storage elements , 1992 .

[14]  Yashwant K. Malaiya,et al.  Antirandom testing: getting the most out of black-box testing , 1995, Proceedings of Sixth International Symposium on Software Reliability Engineering. ISSRE'95.

[15]  Anura P. Jayasumana,et al.  Behavior of faulty double BJT BiCMOS logic gates , 1992 .

[16]  D.,et al.  Data-feedthrough faults in circuits using unclocked storage elements , 1994 .

[17]  S. M. Menon,et al.  Modelling and analysis of bridging faults in emitter-coupled logic (ECL) circuits , 1993 .

[18]  Yashwant K. Malaiya,et al.  ROBUST: a next generation software reliability engineering tool , 1995, Proceedings of Sixth International Symposium on Software Reliability Engineering. ISSRE'95.

[19]  Yashwant K. Malaiya,et al.  Enhancing accuracy of software reliability prediction , 1993, Proceedings of 1993 IEEE International Symposium on Software Reliability Engineering.

[20]  Yashwant K. Malaiya,et al.  On input profile selection for software testing , 1994, Proceedings of 1994 IEEE International Symposium on Software Reliability Engineering.

[21]  N. Karunanithi,et al.  Predictability of software-reliability models , 1992 .

[22]  Anura P. Jayasumana,et al.  Input pattern classification for transistor level testing of BiCMOS circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[23]  S. M. Menon,et al.  Manifestations of faults in single- and double-BJT BiCMOS logic gates , 1995 .

[24]  Anura P. Jayasumana,et al.  Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

[25]  A.P. Jayasumana,et al.  A bipartite, differential I/sub DDQ/ testable static RAM design , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.