TECHNOLOGY Design and Performance analysis of Low power CMOS Op-Amp

This paper proposes a low power CMOS operational amplifier which operates at 1.8 V power supply. The unique behavior of the MOS transistors in sub-thres hold region not only allows a designer to work at l ow input bias current but also at low voltage. While operating th e device at weak inversion results low power dissip ation but dynamic range is degraded. Designing of two-stage Op-Amp is a multi-dimensional optimization problem where optimization of one or more parameters may easily r esult into degradation of others. The Op-Amp is des igned to exhibit a unity gain frequency of 17.3 MHz and exh ibits a gain of 62.04dB. The proposed design uses a smaller compensation capacitor (CC), which improves the slew rate and also, benefits for the area of compensat ion circuit. In order to verify the viability two-stage Op-Amp a t SCNO 180 nm CMOS technology is designed and verified and power consumption is reduced.