Design of m-out-of-n bit-voters

Several synthesis methods for m-out-of-n bit-voting networks are described, and the costs of the resultant designs are compared. In the special case of majority voting (with gate count used as the cost index), it is shown that a multiplexer-based design method yields the best realizations for small n, while designs based on selection networks are most efficient when n is large. Other design techniques are offered that might be more efficient with particular technologies or when certain standard building blocks are to be used in the hardware realization. Most of these designs can be extended to the general case of unequal vote weights (weighted voting).<<ETX>>