Mechanical characterization of residual stress around TSV through instrumented indentation algorithm

Today, copper is the best material for TSV (through silicon via) filling because it can fill a large structural volume and it has good electrical performance. Nevertheless, copper-filled TSVs experience many reliability problems, the most serious of which are the stress-induced issues that can be large enough to cause interfacial fracture or delamination of complex interfaces. Many studies have been conducted to characterize the residual stress around TSV using direct experimental measurement, finite element simulation, and microstructural analysis. The experimental approach is very useful in its speed and direct compatibility with the process, but they have their own limitations to adapt to every case. Nanoinstrumented indentation testing, on the other hand, has many advantages: easy sample preparation and simple algorithms lead to a simple characterization of the micropartial stress between samples with the load difference at the same indentation depth. Here we introduce an algorithm to measure the micropartial residual stress in the copper area (the TSV itself) using conventional NIT (nanoinstrumented indentation testing). We used in-situ SEM (scanning electron microscope) indentation to characterize more accurately the keep-out zone in the silicon area (around TSV), even in very minute areas. Our study is useful in reliability-based quantitative design by defining keep-out zones below several micrometers between TSVs and other transistor-level devices.

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