Mapping 3-D IIR digital filter onto systolic arrays

We present here an efficient systolic implementation for 3-D IIR digital filters. The systolic implementation is obtained by using an algebraic mapping technique. This new mapping technique gives us the choice to mix pipelined variables and broadcast variables. We also determine, through the mapping method, the buffer sizes, the direction of variables propagations and the data feeding and extracting points. The resultant systolic array implementation is a modular structure composed of 2-D filter modules connected by simple buffers. This new systolic implementation is regular, modular and amenable to VLSI Implementation.

[1]  Charles E. Leiserson,et al.  Optimizing synchronous systems , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[2]  Monica S. Lam,et al.  A Transformational Model of VLSI Systolic Design , 1985, Computer.

[3]  Gene H. Golub,et al.  Matrix computations , 1983 .

[4]  Laurence A. Wolsey,et al.  Integer and Combinatorial Optimization , 1988, Wiley interscience series in discrete mathematics and optimization.

[5]  Patrice Quinton,et al.  The systematic design of systolic arrays , 1987 .

[6]  Maher A. Sid-Ahmed.  A systolic realization for 2-D digital filters , 1989, IEEE Trans. Acoust. Speech Signal Process..

[7]  Naresh R. Shanbhag,et al.  An improved systolic architecture for 2-D digital filters , 1991, IEEE Trans. Signal Process..

[8]  T. Kailath,et al.  Array architectures for iterative algorithms , 1987, Proceedings of the IEEE.

[9]  Paul Van Dooren,et al.  Systolic algorithms for digital signal processing , 1988 .

[10]  Pat Hanrahan,et al.  Volume Rendering , 2020, Definitions.

[11]  Peter R. Cappello,et al.  Digital Signal Processing Applications of Systolic Algorithms , 1981 .

[12]  Andreas Antoniou,et al.  VLSI Implementation of Digital FIlters , 2018, Passive, Active, and Digital Filters.

[13]  Andreas Antoniou,et al.  Systolic implementation of digital filters , 1992, Multidimens. Syst. Signal Process..

[14]  Peter R. Cappello,et al.  Scheduling a system of nonsingular affine recurrence equations onto a processor array , 1989, J. VLSI Signal Process..

[15]  David S. Watkins,et al.  Fundamentals of matrix computations , 1991 .

[16]  D.I. Moldovan,et al.  On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[17]  P. Quinton.  Automatic synthesis of systolic arrays from uniform recurrent equations , 1984, ISCA 1984.

[18]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[19]  Edward J. Wegman,et al.  Statistical Signal Processing , 1985 .

[20]  Richard M. Karp,et al.  The Organization of Computations for Uniform Recurrence Equations , 1967, JACM.