A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 psrms jitter
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T. Cho | Li Lin | Chih-Wei Yao | B. Nissim | Himanshu Arora
[1] Ping-Ying Wang,et al. A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[2] Matthew Z. Straayer,et al. A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.