Heterogeneous redundancy for fault and defect tolerance with complexity independent area overhead

The continuous increase in digital system complexity is raising the area cost of redundancy-based fault and defect tolerance. This paper introduces a technique for heterogeneous redundancy in control path and datapath circuitry that provides high reliability with area overhead that is independent of system complexity. Small amounts of circuit-specific reconfigurable logic are finely integrated with fixed-logic circuitry to provide fine-grained heterogeneous fault and defect tolerance. Results reveal that the technique is effective for a variety of circuits, providing high reliability with a constant magnitude area overhead that is independent of system complexity.

[1]  Miodrag Potkonjak,et al.  Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Jason Cong,et al.  Acyclic Multi-Way Partitioning of Boolean Networks , 1994, 31st Design Automation Conference.

[3]  Charles E. Stroud,et al.  Dynamic fault tolerance in FPGAs via partial reconfiguration , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[4]  Melvin A. Breuer,et al.  Roving Emulation as a Fault Detection Mechanism , 1986, IEEE Transactions on Computers.

[5]  John Lach,et al.  Designing, Scheduling, and Allocating Flexible Arithmetic Components , 2003, FPL.

[6]  Charles E. Stroud,et al.  Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).