SI-Aware Vias and Contact Pads Layouts and L--R Equalization Technique for 12 Gb/s Backplane Serial I/O Interconnections

With increasing demand on higher performance for high-speed blade servers, the signal integrity aware (SI-aware) layouts and equalization have been attributed as the critical techniques to improve the electrical performance. This paper describes the SI-aware layouts of patterned ground and capsule-shaped antipad to enhance the connector performance. Besides, a new differential equalizer by taking advantage of differential via-stubs is proposed to restore the deteriorated eye diagram. Their application of a 117.5-cm SATA-II links demonstrates significant improvement in eye height and timing jitter. Furthermore, a viable approach is suggested to successfully reopen the eyes when the data rate increases from the current 3 to 12 Gb/s. The measurement results are also provided to validate the proposed design concepts.

[1]  Wansoo Nah,et al.  Pad shape effects on high frequency signal transfer characteristics , 2008, 2008 Electrical Design of Advanced Packaging and Systems Symposium.

[2]  Sung-Ho Joo,et al.  Resistively-Terminated Via-Stubs for Signal Integrity Improvement in the Semiconductor Test Board , 2007, 2007 Korea-Japan Microwave Conference.

[3]  Wei-Da Guo,et al.  Design of Wideband Impedance Matching for Through-Hole Via Transition Using Ellipse-Shaped Anti-Pad , 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

[4]  William Plowden.  The Compact , 2003 .

[5]  Joungho Kim,et al.  A compact, low-cost, and wide-band passive equalizer design using multi-layer PCB parasitics , 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.

[6]  Bohn Stafleu van Loghum,et al.  Online … , 2002, LOG IN.

[7]  Sang-Hoon Lee,et al.  Signal Integrity Improvements of a MEMS Probe Card Using Back-Drilling and Equalizing Techniques , 2011, IEEE Transactions on Instrumentation and Measurement.

[8]  Jinghan Yu,et al.  Analysis of Via Capacitance in Arbitrary Multilayer PCBs , 2007, IEEE Transactions on Electromagnetic Compatibility.

[9]  Ruey-Beei Wu,et al.  Fast Methodology for Determining Eye Diagram Characteristics of Lossy Transmission Lines , 2009, IEEE Transactions on Advanced Packaging.

[10]  H. W. Johnson.  High-speed backplane connectors , 2011, 2011 IEEE International Symposium on Electromagnetic Compatibility.

[11]  Jun Fan,et al.  Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions , 2010, IEEE Transactions on Electromagnetic Compatibility.

[12]  Ruey-Beei Wu,et al.  SI-aware layout and equalizer design to enhance performance of high-speed links in blade servers , 2011, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems.

[13]  Sangwook Han,et al.  Impact of pad de-embedding on the extraction of interconnect parameters , 2006, 2006 IEEE International Conference on Microelectronic Test Structures.

[14]  Wei-Da Guo,et al.  Reflection Enhanced Compensation of Lossy Traces for Best Eye-Diagram Improvement Using High-Impedance Mismatch , 2008, IEEE Transactions on Advanced Packaging.