An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture

Reconfigurable computing is becoming increasingly attractive for many applications. It involves the use of reconfigurable logic devices (RLDs). RLDs are classified as the fine-grained or coarse-grained type on the basis of their basic logic cell architecture. In general, each architecture has its own merit; therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In this paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and also develop technology mapping tool. Its key feature is the variable granularity being a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. As a result, critical path delay, and number of configuration memory bits are reduced by 49.7%, and 48.5%, respectively, in the benchmark circuits. In addition, when implementing DSP benchmarks on trials, the result is comparable with the highest performance processors today.