A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations

To reduce the time-to-market and photomask cost for advanced process technologies, metal-only engineering change order (ECO) has become a practical and attractive solution to handle incremental design changes. Due to limited spare cells in metal-only ECO, the new added netlist may often violate the input-slew and output-loading constraints and, in turn, delay or even fail the timing closure. This paper presents a framework, named metal-only ECO slew/cap solver (MOESS), to resolve the input-slew and output-loading violations by connecting spare cells onto the violated nets as buffers. MOESS performs two buffer-insertion schemes in a sequential manner to first minimize the number of inserted buffers and then resolve timing violations, if any. The experimental results based on industrial designs demonstrate that MOESS can resolve more violations with fewer inserted buffers and less central processing unit runtime compared to an electronic design automation vendor's solution.

[1]  Andrew B. Kahng,et al.  Minimum-buffered routing of non-critical nets for slew rate and reliability control , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[2]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[3]  Yao-Wen Chang,et al.  ECO Timing Optimization Using Spare Cells and Technology Remapping , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Sadiq M. Sait,et al.  VLSI Physical Design Automation - Theory and Practice , 1995, Lecture Notes Series on Computing.

[5]  Jiang Hu,et al.  Buffer insertion with adaptive blockage avoidance , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Yao-Wen Chang,et al.  ECO timing optimization using spare cells , 2007, ICCAD 2007.

[7]  Noel Menezes,et al.  Repeater scaling and its impact on CAD , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Shiyan Hu,et al.  Fast Algorithms for Slew-Constrained Minimum Cost Buffering , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Shantanu Dutt,et al.  Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[10]  Shih-Chieh Chang,et al.  Spare Cells With Constant Insertion for Engineering Change , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Weiping Shi,et al.  A fast algorithm for optimal buffer insertion , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Yu-Min Kuo,et al.  Engineering change using spare cells with constant insertion , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[13]  Yih-Lang Li,et al.  An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Artur Balasinski Optimization of sub-100-nm designs for mask cost reduction , 2004 .

[15]  Jason Cong,et al.  An implicit connection graph maze routing algorithm for ECO routing , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[16]  Peter J. Osler Placement driven synthesis case studies on two sets of two chips: hierarchical and flat , 2004, ISPD '04.