FPGA Implementation Of DWT-SPIHT Algorithm For Image Compression

The main objective of the paper is to compress the image while transferring it from one end to the other, storage etc. This paper focuses on a memory efficient FPGA implementation for SPIHT (Set Partitioning in Hierarchical Trees) image compression technique. While compressing the image the wavelet transform converts the image into its wavelet coefficients. The SPIHTencoder receives the coefficient value and convert it into the bit stream. Then the SPIHT decoding and inverse wavelet transform will be performed to reconstruct the original image. Because of Poor image quality reconstruction, we are enhancing DCT to Discrete wavelet transform and EBCOT Encoding to SPIHT Encoding. These techniques are implemented on 2-D images and we can validate such compression algorithm by calculating PSNR (peak signal to noise ratio), MSE (Mean square error) and CR(Compression ratio). A hardware realization is done in a Xilinx 10.1 device and The improved algorithm keeps the high SNR, increases the speed greatly and reduces the size of the needed storage space.

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