SEU fault tolerance in artificial neural networks

In this paper we investigate the robustness of Artificial Neural Networks when encountering transient modification of information bits related to the network operation. These kinds of faults are likely to occur as a consequence of interaction with radiation. Results of tests performed to evaluate the fault tolerance properties of two different digital neural circuits are presented.

[1]  Kiyotoshi Matsuoka,et al.  Noise injection into inputs in back-propagation learning , 1992, IEEE Trans. Syst. Man Cybern..

[2]  D. Jacquet,et al.  Design of a digital neural chip: application to optical character recognition by neural network , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[3]  Joan Cabestany,et al.  Digital VLSI implementation of a neural processor , 1991, [1991 Proceedings] 6th Mediterranean Electrotechnical Conference.

[4]  Bernard Widrow,et al.  Sensitivity of feedforward neural networks to weight errors , 1990, IEEE Trans. Neural Networks.

[5]  Alan F. Murray.  Multilayer Perceptron Learning Optimized for On-Chip Implementation: A Noise-Robust System , 1992, Neural Computation.

[6]  T. Chapuis,et al.  Seu And Latch-up Results For Sparc Processors , 1993, 1993 IEEE Radiation Effects Data Workshop.

[7]  Kishan G. Mehrotra,et al.  Training techniques to obtain fault-tolerant neural networks , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[8]  S. Tam,et al.  An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapses , 1990, International 1989 Joint Conference on Neural Networks.

[9]  M. R. Sweet,et al.  Radiation exposure effects on the performance of an electrically trainable artificial neural network (ETANN) , 1993 .

[10]  Simon R. Jones,et al.  Learning in linear systolic neural network engines: analysis and implementation , 1994, IEEE Trans. Neural Networks.

[11]  Petri Koistinen,et al.  Using additive noise in back-propagation training , 1992, IEEE Trans. Neural Networks.

[12]  Alan F. Murray,et al.  Enhanced MLP performance and fault tolerance resulting from synaptic weight noise during training , 1994, IEEE Trans. Neural Networks.

[13]  H. Graf,et al.  A CMOS associative memory chip based on neural networks , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[14]  Michel Weinfeld,et al.  Integrated artificial neural networks: components for higher level architectures with new properties , 1989, NATO Neurocomputing.

[15]  Robert I. Damper,et al.  Determining and improving the fault tolerance of multilayer perceptrons in a pattern-recognition application , 1993, IEEE Trans. Neural Networks.

[16]  Marc Duranton,et al.  Lneuro 1.0: a piece of hardware LEGO for building neural network systems , 1992, IEEE Trans. Neural Networks.

[17]  Michel Verleysen,et al.  Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm , 1989 .