Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors

An area-efficient dynamic thermal management (DTM) unit using multiplying delay-locked loop (MDLL) with shared DLL scheme is proposed for per-core DTM in many-core processors. The proposed DTM unit consists of a MDLL and a shared-DLL-based temperature sensor. The shared DLL takes part in both temperature sensing and frequency scaling while reducing the size of whole DTM unit. The area is reduced by 54.4% compared to the design in which a phase-locked loop (PLL) is used without any optimization scheme.

[1]  Hsien-Hsin S. Lee,et al.  Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory , 2010, IEEE Custom Integrated Circuits Conference 2010.

[2]  Margaret Martonosi,et al.  Techniques for Multicore Thermal Management: Classification and New Exploration , 2006, ISCA 2006.

[3]  Fabien Clermidy,et al.  Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[4]  B. Razavi A study of injection locking and pulling in oscillators , 2004, IEEE Journal of Solid-State Circuits.

[5]  R. Kumar,et al.  An Integrated Quad-Core Opteron Processor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[7]  William J. Dally,et al.  The GPU Computing Era , 2010, IEEE Micro.

[8]  Pradeep Dubey,et al.  Larrabee: A Many-Core x86 Architecture for Visual Computing , 2009, IEEE Micro.

[9]  Kyoungho Woo,et al.  Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  Peter R. Kinget,et al.  A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[11]  Chulwoo Kim,et al.  A low-power programmable DLL-based clock generator with wide-range anti-harmonic lock , 2009, 2009 International SoC Design Conference (ISOCC).

[12]  Zhiyi Yu,et al.  A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.