The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style
暂无分享,去创建一个
[1] Andrew Wolfe,et al. A fast asynchronous Huffman decoder for compressed-code embedded processors , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[2] Jianwei Liu,et al. Dynamic logic in four-phase micropipelines , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[3] Alain J. Martin,et al. Three generations of asynchronous microprocessors , 2003, IEEE Design & Test of Computers.
[4] Siamak Mohammadi,et al. AMULET3i-an asynchronous system-on-chip , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).
[5] Steven M. Nowick,et al. Modeling and design of asynchronous circuits , 1999, Proc. IEEE.
[6] M.A. Horowitz,et al. Skew-tolerant domino circuits , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[7] Peter A. Beerel,et al. High-speed QDI asynchronous pipelines , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.
[8] Ivan E. Sutherland,et al. Two FIFO ring performance experiments , 1999, Proc. IEEE.
[9] Andrew M Lines,et al. Pipelined Asynchronous Circuits , 1998 .
[10] Peter A. Beerel,et al. High-speed non-linear asynchronous pipelines , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[11] Carl Sechen,et al. Clock-delayed domino for adder and combinational logic design , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.
[12] Paul I. Pénzes,et al. The design of an asynchronous MIPS R3000 microprocessor , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.
[13] B. Chappell. The fine art of IC design , 1999 .
[14] Kenneth L. Shepard,et al. Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..
[15] Ad M. G. Peeters,et al. An asynchronous low-power 80C51 microcontroller , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[16] Ran Ginosar,et al. Relative timing , 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[17] Ad M. G. Peeters,et al. Single-rail handshake circuits , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.
[18] Luciano Lavagno,et al. Lazy transition systems: application to timing optimization of asynchronous circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[19] Eby G. Friedman,et al. System Timing , 2000, The VLSI Handbook.
[20] Ivan E. Sutherland,et al. Micropipelines , 1989, Commun. ACM.
[21] Vinod Narayanan,et al. Static timing analysis for self resetting circuits , 1996, Proceedings of International Conference on Computer Aided Design.
[22] Giovanni De Micheli,et al. Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] Steven M. Nowick,et al. The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[24] Steven M. Nowick,et al. The design of high-throughput asynchronous pipelines , 2002 .
[25] Peter A. Beerel,et al. High-performance asynchronous pipeline circuits , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[26] Paul Day,et al. Investigation into micropipeline latch design styles , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[27] Ivan E. Sutherland,et al. GasP: a minimal FIFO control , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.
[28] Ted Eugene Williams,et al. Self-timed rings and their application to division , 1992 .
[29] Mark Horowitz,et al. A zero-overhead self-timed 160-ns 54-b CMOS divider , 1991 .
[30] D. Heidel,et al. Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[31] Peter A. Beerel,et al. Single-track asynchronous pipeline templates using 1-of-N encoding , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[32] Ran Ginosar,et al. A doubly-latched asynchronous pipeline , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.
[33] Sorin A. Huss,et al. VLSI system design using asynchronous wave pipelines: a 0.35 /spl mu/m CMOS 1.5 GHz elliptic curve public key cryptosystem chip , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).
[34] Steven M. Nowick,et al. High-throughput asynchronous pipelines for fine-grain dynamic datapaths , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).
[35] Ran Ginosar,et al. RAPPID: an asynchronous instruction length decoder , 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[36] Ralph K. Cavin,et al. A 250-MHz wave pipelined adder in 2-/spl mu/m CMOS , 1994 .
[37] Pradip Bose,et al. Synchronous interlocked pipelines , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.