Layout synthesis of combinational blocks from behavioral hardware descriptions

A CAD tool that generates the layout of a combinational circuit from a behavioral hardware description language (HDL) representation is presented. A minimized transistor netlist is synthesised. Simulated annealing is used to determine the optimal placement and routing of each transistor group. As input, the system accepts VHSIC hardware description language (VHDL), VERILOG, truth table, and Boolean equation descriptions. For simulation purposes SPICE models of the circuit are also generated.<<ETX>>

[1]  Akihiro Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC.

[2]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[3]  Takao Uehara,et al.  Optimal Layout of CMOS Functional Arrays , 1978, 16th Design Automation Conference.

[4]  Ron Y. Pinter,et al.  Optimal Chaining of CMOS Transistors in a Functional Cell , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  A. Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC '71.

[6]  P. W. Kollaritsch,et al.  TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout , 1984, ESSCIRC '84: Tenth European Solid-State Circuits Conference.

[7]  Charles J. Poirier.  Excellerator: custom CMOS leaf cell layout generator , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Donald G. Baltus,et al.  SOLO: a generator of efficient layouts from optimized MOS circuit schematics , 1988, DAC '88.

[9]  Joseph Y.-T. Leung,et al.  An Optimal Solution for the Channel-Assignment Problem , 1979, IEEE Transactions on Computers.

[10]  Carl Sechen,et al.  VLSI Placement and Global Routing Using Simulated Annealing , 1988 .

[11]  Chak-Kuen Wong,et al.  On VHV-routing in channels with irregular boundaries , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Huang,et al.  AN EFFICIENT GENERAL COOLING SCHEDULE FOR SIMULATED ANNEALING , 1986 .

[13]  Takashi Satoh,et al.  A high packing density module generator for CMOS logic cells , 1988, DAC '88.

[14]  Uehara,et al.  Optimal Layout of CMOS Functional Arrays , 1981 .