On a Power-Delay Product for a Heterogeneous MDD for ECFN Machine

This paper analyzes a power-delay product for a HMDD for an ECFN (Heterogeneous Multi-valued Decision Diagram for Encoded Characteristic Function for Non-zero outputs) Machine that emulates the HMDD for ECFN. First, we introduce the HMDD for ECFN representing the multi-output logic function. Then, we show an architecture for the HMDD for ECFN machine. Next, we obtain the delay time and the power consumption for the HMDD for ECFN machine using the MCNC benchmark function. Finally, we analyze the power-delay product for the HMDD for ECFN machine. Compared with the Intel’s Core i5, whose clock frequency is 2.4 GHz, as for the delay time, the HMDD for ECFN machine is 1.40-4.27 times shorter than Core i5, and as for the power-delay product, it is 15.1-46.6 times smaller.

[1]  Tsutomu Sasao.  Compact SOP representations for multiple-output functions-an encoding method using multiple-valued logic , 2001, Proceedings 31st IEEE International Symposium on Multiple-Valued Logic.

[2]  K. Driesen,et al.  Accurate indirect branch prediction , 1998, Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235).

[3]  Tsutomu Sasao,et al.  Average path length of binary decision diagrams , 2005, IEEE Transactions on Computers.

[4]  Nakahara Hiroki,et al.  On a Prefetching Heterogeneous MDD Machine , 2010 .

[5]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[6]  Tsutomu Sasao,et al.  A Packet Classifier Using a Parallel Branching Program Machine , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[7]  Tsutomu Sasao,et al.  A hardware simulation engine based on decision diagrams , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[8]  Tiziano Villa,et al.  Multi-valued decision diagrams: theory and applications , 1998 .

[9]  T. Sasao,et al.  Realization of sequential circuits by look-up table rings , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[10]  Raymond T. Boute,et al.  The binary decision machine as programmable controller , 1976 .

[11]  Shinobu Nagayama,et al.  Compact BDD Representations for Multiple-Output Functions and Their Application , 2001 .

[12]  P.P. Gelsinger,et al.  Microprocessors for the new millennium: Challenges, opportunities, and new frontiers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[13]  Shinobu Nagayama,et al.  Compact representations of logic functions using heterogeneous MDDs , 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

[14]  Tsutomu Sasao,et al.  A Comparison of Architectures for Various Decision Diagram Machines , 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.

[15]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[16]  Shinobu Nagayama,et al.  On the optimization of heterogeneous MDDs , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Tsutomu Sasao,et al.  A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions , 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

[18]  Paul J. Zsombor-Murray,et al.  Binary- Decision -Based Programmable Controllers Part I , 1983 .

[19]  Daniel Mange,et al.  A High-Level-Language Programmable Controller , 1986, IEEE Micro.