Total Ionizing Dose Effects on FinFET-Based Capacitor-Less 1T-DRAMs

We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T-DRAM cells programmed with back-gate pulses are quite sensitive to total ionizing dose radiation, with the memory sensing margin and retention time decreasing significantly with increasing dose. In contrast, the sensing margin and retention time show high tolerance to total ionizing dose irradiation when the 1T-DRAM cells are programmed via GIDL. The sensing margin increases significantly with decreasing gate length for 1T-DRAM cells programmed via GIDL. We conclude that capacitor-less 1T-DRAMs programmed via GIDL are strong candidates for embedded memory applications for ultimately scaled CMOS devices in high-TID applications.

[1]  Jin-Woo Han,et al.  Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM) , 2009 .

[2]  E. Zhang,et al.  Research on metastable electron traps in the modified SOI materials induced by Si ion implantation , 2008 .

[3]  Daniel M. Fleetwood,et al.  Generation of metastable electron traps in the near interfacial region of SOI buried Oxides by ion implantation and their effect on device properties , 2003 .

[4]  Y. Watanabe,et al.  Offset compensating bit-line sensing scheme for high density DRAM's , 1994 .

[6]  J.-P. Raskin,et al.  Dependence of finFET RF performance on fin width , 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[7]  Denis Flandre,et al.  A new memory effect (MSD) in fully depleted SOI MOSFETs , 2005 .

[8]  Shyh-Chyi Wong,et al.  An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET , 2001 .

[9]  A. Paccagnella,et al.  Microdose and Breakdown Effects Induced by Heavy Ions on Sub 32-nm Triple-Gate SOI FETs , 2008, IEEE Transactions on Nuclear Science.

[10]  Martin L. Green,et al.  Precursor ion damage and angular dependence of single event gate rupture in thin oxides , 1998 .

[11]  R. Stahlbush.  Electron and hole trapping in the buried oxide of Unibond wafers , 1997 .

[12]  R.A. Reed,et al.  Scaling and soft errors: Moore of the same for SOI ? , 2008, 2008 IEEE International SOI Conference.

[13]  R. L. Pease,et al.  An improved standard total dose test for CMOS space electronics , 1989 .

[14]  T. Tanaka,et al.  A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory , 2006, IEEE Transactions on Electron Devices.

[15]  H. L. Hughes,et al.  Hole and electron trapping in ion implanted thermal oxides and SIMOX , 2000 .

[16]  B. Vermeire,et al.  Band-to-Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices , 2007, IEEE Transactions on Nuclear Science.

[17]  R. Degraeve,et al.  A Statistical Approach to Microdose Induced Degradation in FinFET Devices , 2009, IEEE Transactions on Nuclear Science.

[18]  J.A. Felix,et al.  Radiation Effects in MOS Oxides , 2008, IEEE Transactions on Nuclear Science.

[19]  C. Bassin,et al.  Soft Error Performance of Z-RAM Floating Body Memory , 2006, 2006 IEEE international SOI Conferencee Proceedings.

[20]  P. Paillet,et al.  Physical characterization of electron trapping in Unibond(R) oxides , 1997 .

[21]  En Xia Zhang,et al.  Fin-Width Dependence of Ionizing Radiation-Induced Subthreshold-Swing Degradation in 100-nm-Gate-Length FinFETs , 2009, IEEE Transactions on Nuclear Science.

[23]  Tsu-Jae King,et al.  Full/partial depletion effects in FinFETs , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[24]  D. Takashima,et al.  Offset compensating bit-line sensing scheme for high density DRAMs , 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

[25]  Daniel M. Fleetwood,et al.  Hardness assurance for low-dose space applications (MOS devices) , 1991 .

[26]  Daniel M. Fleetwood,et al.  Single event gate rupture in thin gate oxides , 1997 .

[27]  Denis Flandre,et al.  Floating-Body SOI Memory: Concepts, Physics and Challenges , 2009 .

[28]  C. Mazure,et al.  Ultra-scaled Z-RAM cell , 2008, 2008 IEEE International SOI Conference.

[29]  Seo Dong-Il,et al.  Offset-Compensated Direct Sensing and Charge-Recycled Precharge Schemes for Sub-1.0 V High-Speed DRAM's , 2004 .

[30]  Akihiro Nitayama,et al.  Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization , 2009, IEEE Transactions on Electron Devices.