Post global routing crosstalk risk estimation and reduction

Previous approaches for crosstalk synthesis often fail to achieve satisfactory results due to limited routing flexibility. Furthermore, the risk tolerance bounds partitioning problem critical for constrained optimization has not been adequately addressed. This paper presents the first approach for crosstalk risk estimation and reduction at the global (instead of detailed) routing level. It quantitatively defines and estimates the risk of each routing region using a graph-based optimization approach and globally adjusts routes of nets for risk reduction. At the end of the entire optimization process, a risk-free global routing solution is obtained together with partitions of nets' risk tolerance bounds which reflect the crosstalk situation of the chip. The proposed approach has been implemented and tested on CBL/NCSU benchmarks and the experimental results are very promising.

[1]  H. H. Chen,et al.  Wiring And Crosstalk Avoidance In Multi-chip Module Design , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[2]  Dhanistha Panyasak,et al.  Circuits , 1995, Annals of the New York Academy of Sciences.

[3]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[4]  C. L. Liu,et al.  Minimum crosstalk channel routing , 1993, ICCAD.

[5]  Ernest S. Kuh,et al.  A spacing algorithm for performance enhancement and cross-talk reduction , 1993, ICCAD.

[6]  Martin D. F. Wong,et al.  An optimal layer assignment algorithm for minimizing crosstalk for three layer VHV channel routing , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[7]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Martin D. F. Wong,et al.  A New Algorithm for Floorplan Design , 1986, 23rd ACM/IEEE Design Automation Conference.

[9]  David K. Smith Network Flows: Theory, Algorithms, and Applications , 1994 .

[10]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.

[11]  Hai Zhou,et al.  An optimal algorithm for river routing with crosstalk constraints , 1996, Proceedings of International Conference on Computer Aided Design.

[12]  Dongsheng Wang,et al.  Performance-driven interconnect global routing , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

[13]  Hai Zhou,et al.  Crosstalk-constrained maze routing based on Lagrangian relaxation , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[14]  Alberto L. Sangiovanni-Vincentelli,et al.  Techniques for crosstalk avoidance in the physical design of high-performance digital systems , 1994, ICCAD.

[15]  Dongsheng Wang,et al.  Post global routing crosstalk risk estimation and reduction , 1996, ICCAD 1996.

[16]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[17]  Ravindra K. Ahuja,et al.  Network Flows: Theory, Algorithms, and Applications , 1993 .