A Memory-Efficient FPGA-based Classification Engine

Packet classification is one of the most important enabling technologies for next generation network services. Even though many multi-dimensional classification algorithms have been proposed, most of them are precluded from commercial equipments due to their high memory requirements. In this paper, we present an efficient packet classification scheme, implemented in reconfigurable hardware, called Dual Stage Bloom Filter Classification Engine (2sBFCE). 2sBFC comprises of an innovative 5-field search scheme that decomposes multi-field classification rules into internal single-field rules which are combined using multi-level Bloom filters. The design of 2sBFCE is optimized for the common case based on analysis of real world classification databases. The FPGA implementation of the proposed scheme handles 4 K rules, with very small memory requirements, while supporting network streams at a rate of 2 Gbps in the worst case, and more than 6 Gbps in the average case.

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