A watermarking system for IP protection by buffer insertion technique

In this paper, we introduce a kind of watermarking system for IP protection (IPP). The copyright is encrypted and then embedded into the design as the watermark in buffer insertion stage. This watermarking technique can identify the design copyright uniquely, and is fit for both ASIC using standard cells and full-custom design. We have evaluated the technique on several testing designs, the inserted results show that the watermarking process achieves 100% success causing little overhead on design performance. Extraction and identification process of the watermark is also analyzed. The watermark embedded is hard to be found out and tampered away, and the technique can be integrated into EDA tools for manufacturing

[1]  Miodrag Potkonjak,et al.  Behavioral synthesis techniques for intellectual property protection , 2005, TODE.

[2]  Daniela De Venuto,et al.  International Symposium on Quality Electronic Design , 2005, Microelectronics Journal.

[3]  Miodrag Potkonjak,et al.  Behavioral synthesis techniques for intellectual property protection , 2005, TODE.

[4]  Tingyuan Nie,et al.  A watermarking system for IP protection by a post layout incremental router , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[5]  Jason Cong,et al.  An interconnect-centric design flow for nanometer technologies , 2001, Proc. IEEE.

[6]  Miodrag Potkonjak,et al.  Constraint-based watermarking techniques for design IP protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Jason Cong,et al.  Intellectual property protection by watermarking combinational logic synthesis solutions , 1998, ICCAD '98.

[8]  Jason Cong,et al.  Challenges and Opportunities for Design Innovations in Nanometer Technologies , 1998 .

[9]  Jason Cong,et al.  Buffer block planning for interconnect planning and prediction , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Jason Cong,et al.  Intellectual property protection by watermarking combinational logic synthesis solutions , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[11]  Spyros Tragoudas,et al.  Rewiring for watermarking digital circuit netlists , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.