On the differential nonlinearity of time-to-digital converters based on delay-locked-loop delay lines

A theoretical analysis of the effects of the delay-line differential nonlinearity (DNL) on the typical performance parameters of high-resolution time-to-digital converters (TDCs) based on delay-locked-loop (DLL) delay lines has been developed. The theoretical study is based on the knowledge of the delay-line nonlinearity values that can be measured, with the desired precision, by means of a statistical code-density test. In particular, the effects on the TDC time resolution and error standard deviation curve as a function of the measured time interval are investigated. An a posteriori linearization technique, consisting in a proper correction of the TDC readouts, is then analyzed and its advantages are theoretically demonstrated. Finally, the theoretical results are superimposed on experimental data coming from a real TDC. The measured deviations from the ideal behavior are thus justified and can just be ascribed to the delay-line nonlinearity.

[1]  Ryszard Szplet,et al.  Interpolating time counter with 100 ps resolution on a single FPGA device , 2000, IEEE Trans. Instrum. Meas..

[2]  Roberto Roncella,et al.  A 250-ps time-resolution CMOS multihit time-to-digital converter for nuclear physics experiments , 1999 .

[3]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[4]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.

[5]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[6]  Luca Fanucci,et al.  Non-linearity reduction technique for delay-locked delay-lines , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[7]  Y. Arai,et al.  A time digitizer CMOS gate-array with a 250 ps time resolution , 1996, IEEE J. Solid State Circuits.

[8]  M. Mota,et al.  A high-resolution time interpolator based on a delay locked loop and an RC delay line , 1999, IEEE J. Solid State Circuits.

[9]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines for the digitization of short time intervals , 1993 .

[10]  Timo Rahkonen,et al.  An Integrated Digital CMOS Time-to-Digital Converter with Sub-Gate-Delay Resolution , 2000 .

[11]  Pietro Andreani,et al.  Multihit multichannel time-to-digital converter with /spl plusmn/1% differential nonlinearity and near optimal time resolution , 1998 .

[12]  S. Kleinfelder,et al.  MTD132-a new subnanosecond multi-hit CMOS time-to-digital converter , 1991 .

[13]  Ryszard Szplet,et al.  Nonlinearity correction of the integrated time-to-digital converter with direct coding , 1996 .

[14]  Bruno O. Shubert,et al.  Random variables and stochastic processes , 1979 .