CMOS sense amplifier-based flip-flop with two N-C/sup 2/MOS output latches

By replacing the NAND SR latch at the output stage of a conventional sense amplifier-based flip-flop (SAFF) by two N-C2MOS latches, the operating speed of the flip-flop is enhanced by 63% and the power-delay-product is reduced by 28%.

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