Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique
暂无分享,去创建一个
Chandra Mohan Reddy Sivappagari | Telugu Maddileti | Govindarajulu Salendra | Telugu Maddileti | Govindarajulu Salendra
[1] K. L. Baishnab,et al. Offset voltage minimization based circuit sizing of CMOS operational amplifier using whale optimization algorithm , 2018 .
[2] Juho Kim,et al. Performance optimization in FinFET-based circuit using TILOS-like gate sizing , 2016, 2016 International Symposium on Integrated Circuits (ISIC).
[3] M. J. D. Powell,et al. A fast algorithm for nonlinearly constrained optimization calculations , 1978 .
[5] Hiroyuki Kitajima,et al. Chaotic Bursts and bifurcation in Chaotic Neural Networks with Ring Structure , 2001, Int. J. Bifurc. Chaos.
[6] Andrew Lewis,et al. Grey Wolf Optimizer , 2014, Adv. Eng. Softw..
[7] Xuan Zeng,et al. Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Amir Hossein Gandomi,et al. Chaotic bat algorithm , 2014, J. Comput. Sci..
[9] Carl Sechen,et al. Are standalone gate size and VT optimization tools useful? , 2017, 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE).
[10] Rob A. Rutenbar,et al. Computer-Aided Design of Analog Integrated Circuits and Systems , 2002 .
[11] Dervis Karaboga,et al. A modified Artificial Bee Colony (ABC) algorithm for constrained optimization problems , 2011, Appl. Soft Comput..
[12] Sankalap Arora,et al. Chaotic grey wolf optimization algorithm for constrained optimization problems , 2018, J. Comput. Des. Eng..
[13] Stephan Held,et al. Provably Fast and Near-Optimum Gate Sizing , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Mathias Beike,et al. Digital Integrated Circuits A Design Perspective , 2016 .
[15] K. A. Sumithra Devi,et al. Hybrid Partitioning Algorithm for Area Minimization in Circuits , 2015 .
[16] K. L. Baishnab,et al. Automated sizing of low-noise CMOS analog amplifier using ALCPSO optimization algorithm , 2018 .
[17] Azam Beg. Automating the CMOS Gate Sizing for Reduced Power/Energy , 2014, 2014 12th International Conference on Frontiers of Information Technology.
[18] Maneesha Gupta,et al. Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms , 2018, Integr..
[19] Alessandro Girardi,et al. Power constrained design optimization of analog circuits based on physical gm/ID characteristics , 2006, SBCCI '06.
[20] Louis M. Pecora,et al. Synchronizing chaotic systems , 1993, Optics & Photonics.
[21] Kazuyuki Aihara,et al. Combination of Chaotic Neurodynamics with the 2-opt Algorithm to Solve Traveling Salesman Problems , 1997 .
[22] Provas Kumar Roy,et al. Oppositional based grey wolf optimization algorithm for economic dispatch problem of power system , 2017, Ain Shams Engineering Journal.
[23] K. B. Maji,et al. Opposition Harmony Search algorithm based optimal sizing of CMOS analog amplifier circuit , 2015, 2015 International Conference on Science and Technology (TICST).
[24] Esteban Tlelo-Cuautle,et al. An RBF-PSO technique for the rapid optimization of (CMOS) analog circuits , 2018, 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST).
[25] Di He,et al. Chaotic characteristics of a one-dimensional iterative map with infinite collapses , 2001 .
[26] Durbadal Mandal,et al. Optimal sizing of CMOS analog circuits using gravitational search algorithm with particle swarm optimization , 2015, International Journal of Machine Learning and Cybernetics.
[27] Francisco V. Fernández,et al. Fundamentals of Optimization Techniques in Analog IC Sizing , 2014 .
[28] G. Cheng,et al. On the efficiency of chaos optimization algorithms for global optimization , 2007 .
[29] Dongkyung Nam,et al. Parameter optimization of an on-chip voltage reference circuit using evolutionary programming , 2001, IEEE Trans. Evol. Comput..
[30] Xin-She Yang,et al. Chaos-enhanced accelerated particle swarm optimization , 2013, Commun. Nonlinear Sci. Numer. Simul..
[31] Vishwani D. Agrawal,et al. Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation , 2008, 21st International Conference on VLSI Design (VLSID 2008).
[32] David J. Allstot,et al. Sizing of cell-level analog circuits using constrained optimization techniques , 1993 .
[33] M. Madhavi Latha,et al. Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits , 2016 .
[34] José Herskovits,et al. A two-stage feasible directions algorithm for nonlinear constrained optimization , 1981, Math. Program..