Discussion on High Level Synthesis FPGA Design of Camera Calibration

Geometric camera calibration plays a key role in machine vision to detect and measure objects. This work presents the high level synthesis (HLS) design of a camera calibration algorithm on an FPGA. By optimizing the C description, we were able to improve execution performance of the naive implementation by about 1.3–1.5 times. Especially, it was shown that the way of describing multi-dimensional arrays has a large impact on synthesis results. However, the implementation requires more hardware resources than available on the chip. A large amount of arithmetic operations become a bottleneck for FPGA resources due to the calculation of all parameters.