3D/TSV enabling technologies for SOC/NOC: Modeling and design challenges

According to the International Technology Roadmap for Semiconductors (ITRS), the traditional scaling will no longer meet the performance and integration requirements of systems-on-chip (SoC) in the long term. Therefore, new I/O and packaging paradigms are needed. Three-dimensional integration is a promising alternative option to traditional 2D planar chips. 3D integration is mainly restricted by the communication infrastructure between different stacked dies of future multi-core SoC and network-on-chip (NoC). Among several 3D integration technologies, the TSV (Through-Silicon-Via) approach is the most promising one and therefore is the focus of the majority of 3D integration R&D activities. However, there are challenges that should be overcome before the production of TSV-based 3D ICs becomes possible, e.g., electrical modeling challenges, thermal and power challenges, technological challenges, design methodology challenges and CAD tool development challenges.

[1]  Arifur Rahman,et al.  System-level performance evaluation of three-dimensional integrated circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[3]  K.C. Saraswat,et al.  Thermal analysis of heterogeneous 3D ICs with various integration scenarios , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[4]  Junho Lee,et al.  High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package , 2005, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005..

[5]  Joungho Kim,et al.  High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging , 2006, 2006 1st Electronic Systemintegration Technology Conference.

[6]  Joungho Kim,et al.  Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV) , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[7]  Philip G. Emma,et al.  Interconnects in the Third Dimension: Design Challenges for 3D ICs , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[8]  N. Kernevez,et al.  Challenges for 3D IC integration: bonding quality and thermal management , 2007, 2007 IEEE International Interconnect Technology Conferencee.

[9]  Joungho Kim,et al.  Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation , 2007, 2007 International Conference on Electronic Materials and Packaging.

[10]  G. Cibrario,et al.  Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology , 2008 .

[11]  S. Yoon,et al.  High RF performance TSV silicon carrier for high frequency application , 2008, 2008 58th Electronic Components and Technology Conference.

[12]  Eby G. Friedman,et al.  Electrical modeling and characterization of 3-D vias , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[13]  Sherief Reda,et al.  Parametric yield management for 3D ICs: Models and strategies for improvement , 2008, JETC.

[14]  Dimitrios Soudris,et al.  Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology , 2008, Int. J. Reconfigurable Comput..

[15]  S. Mukhopadhyay,et al.  TSV-aware interconnect length and power prediction for 3D stacked ICs , 2009, 2009 IEEE International Interconnect Technology Conference.

[16]  Luca P. Carloni,et al.  Networks-on-chip in emerging interconnect paradigms: Advantages and challenges , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[17]  Joungho Kim,et al.  Through silicon via (TSV) equalizer , 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.

[18]  Hannu Tenhunen,et al.  Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits (ICs) , 2009 .

[19]  Joungho Kim,et al.  Active circuit to through silicon via (TSV) noise coupling , 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.

[20]  E. Friedman,et al.  Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance , 2009, IEEE Transactions on Electron Devices.

[21]  Thierry Lacrevaz,et al.  Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking , 2009, 2009 IEEE International Conference on 3D System Integration.

[22]  Subarna Sinha,et al.  The road to 3D EDA tool readiness , 2009, 2009 Asia and South Pacific Design Automation Conference.

[23]  Tong Zhang,et al.  Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration , 2009, 2009 IEEE International Conference on 3D System Integration.

[24]  Jin-Fu Li,et al.  Is 3D integration an opportunity or just a hype? , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).