The Key Techniques of Automatic Logic Diagrams Generation for High Level Synthesis

The automatic logic diagram generation system discussed in this paper is a subsystem of Practical High Level Design (HLD) System of ASIC——Talent, which is a production of “ninth five year plan” pre investigating scientific research on micro electronics of national defense. By identifying and partitioning the net list, placing logic units and routing signal lines, the subsystem can automatically generate good looking logic diagrams with certain logic circuit functional information. The keystone of our research is to solve the technical problems about production use of automatic logic diagrams generation system. Combining the rule based knowledge denotation with formal algorithm, we propose an efficient method of automatic placement. The theory and method of pattern recognition is applied to solve the automatic routing of logic diagrams and we propose a method of channel routing based on decision tree. The whole rule system is also presented in this paper. Moreover, an detailed partition model is discussed. Two efficient algorithms for multiple way partition of logic diagrams are also implemented: (1) Seed _Expansion algorithm and (2)Iterative Improvement algorithm. The main idea of Seed _Expansion algorithm is a derivative of greedy algorithm and Iterative Improvement algorithm is a modification of traditional min cut algorithm (KL algorithm). Experimental results show that these algorithms have low time complexity and high precision, and they have good effects in application. Based on the above research work, a perfect automatic schematics generator has been constructed. The tool is proven to be correct and stable, and have undergone tens of test examples. It can generate nice and normative logic diagrams quickly. Especially it can solve the logic diagram generation problem of large scale circuits effectively. This contributes greatly to the practicability of the whole design system.