Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization

In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation.

[1]  Asen Asenov,et al.  Statistical TCAD based PDK development for a FinFET technology at 14nm technology node , 2012 .

[2]  Yiming Li,et al.  Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies , 2010, IEEE Transactions on Electron Devices.

[3]  A. Asenov,et al.  Statistical Simulation of Progressive NBTI Degradation in a 45-nm Technology pMOSFET , 2010, IEEE Transactions on Electron Devices.

[4]  Zheng Guo,et al.  The impact of assist-circuit design for 22nm SRAM and beyond , 2012, 2012 International Electron Devices Meeting.

[5]  Asen Asenov,et al.  A 3-D Atomistic Study of Archetypal Double Gate MOSFET Structures , 2002 .

[6]  Andrew R. Brown,et al.  Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology , 2013, IEEE Design & Test.

[7]  Mario G. Ancona,et al.  Density-gradient theory: a macroscopic approach to quantum confinement and tunneling in semiconductor devices , 2011 .

[8]  T. Skotnicki,et al.  An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation , 2008, IEEE Transactions on Electron Devices.

[9]  Dick James,et al.  Intel Ivy Bridge unveiled — The first commercial tri-gate, high-k, metal-gate CPU , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[10]  Andrew R. Brown,et al.  Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs , 2013, IEEE Transactions on Electron Devices.

[11]  Sani R. Nassif,et al.  SRAM device and cell co-design considerations in a 14nm SOI FinFET technology , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[12]  Chris Auth,et al.  22-nm fully-depleted tri-gate CMOS transistors , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[13]  Greg Northrop Design technology co-optimization in technology definition for 22nm and beyond , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[14]  H. Reisinger,et al.  HCI vs. BTI? - Neither one's out , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[15]  C. H. Diaz,et al.  Expanding role of predictive TCAD in advanced technology development , 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

[16]  A. Asenov,et al.  Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs , 2006, IEEE Transactions on Electron Devices.

[17]  Asen Asenov,et al.  Time-Dependent 3-D Statistical KMC Simulation of Reliability in Nanoscale MOSFETs , 2014, IEEE Transactions on Electron Devices.

[18]  O. Rozeau,et al.  28nm FDSOI technology platform for high-speed low-voltage digital applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[19]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[20]  I. Knezevic,et al.  Self-consistent Poisson-Schrödinger-Monte Carlo solver: electron mobility in silicon nanowires , 2010 .

[21]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[22]  Andrew R. Brown,et al.  Statistical variability and reliability in nanoscale FinFETs , 2011, 2011 International Electron Devices Meeting.

[23]  G. Curello,et al.  A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications , 2012, 2012 International Electron Devices Meeting.

[24]  Asen Asenov,et al.  Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells , 2005 .

[25]  Andrew R. Brown,et al.  Use of density gradient quantum corrections in the simulation of statistical variability in MOSFETs , 2010 .

[26]  Andrzej J. Strojwas,et al.  Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  J. Watts Enhancing Productivity by Continuously Improving Standard Compact Models , 2006, IEEE Custom Integrated Circuits Conference 2006.