We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTD's form storage latches, and these are connected by networks consisting of field-effect transistors (FET's), saturated resistors, and RTD's. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FET's alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTD's should operate five times faster when both technologies follow the CMOS design rules.