ACE: A Hierarchical Graphical Interface for Architectural Synthesis

Existing interfaces for high-level synthesis dictate that the synthesis process be iterative rather than interactive. This paper presents an interface tool for architectural synthesis that introduces real-time interaction to high-level synthesis interfaces. ACE makes innovations in the dynamic display of synthesizer transformations and introduces new concepts in input algorithm specification.

[1]  Donald E. Thomas,et al.  The system architect's workbench , 1988, DAC '88.

[2]  Carlo H. Séquin VLSI Design Strategies , 1987 .

[3]  Mario Barbacci,et al.  Instruction set processor specifications (ISPS): The notation and its applications , 1981, IEEE Transactions on Computers.

[4]  Jingfeng Xia Publishers , 1935, Predatory Publishing.

[5]  Donald E. Thomas,et al.  CORAL II: linking behavior and structure in an IC design system , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[6]  Mohamed I. Elmasry,et al.  SPAID: an architectural synthesis tool for DSP custom applications , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[7]  Alice C. Parker,et al.  Tutorial on high-level synthesis , 1988, DAC '88.

[8]  Lightwave Systems Computer-Aided Design of Digital , 1984 .

[9]  H. De Man,et al.  Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.