On the generation of area-time optimal testable adders
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[1] Vinod K. Agarwal,et al. Non-Stuck-At Fault Detection in nMOS Circuits by Region Analysis , 1983, ITC.
[2] Leonidas J. Guibas,et al. Optimal Point Location in a Monotone Subdivision , 1986, SIAM J. Comput..
[3] Rolf Drechsler,et al. A time optimal robust path-delay-fault self-testable adder , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[4] Arthur D. Friedman,et al. Easily Testable Iterative Systems , 1973, IEEE Transactions on Computers.
[5] Wilfried Daehn,et al. A Hardware Approach to Self-Testing of Large Programmable Logic Arrays , 1981, IEEE Transactions on Computers.
[6] John A. Waicukauski,et al. Transition Fault Simulation by Parallel Pattern Single Fault Propagation , 1986, International Test Conference.
[7] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[8] Alberto L. Sangiovanni-Vincentelli,et al. A heuristic algorithm for the fanout problem , 1991, DAC '90.
[9] Kurt Keutzer,et al. Testability properties of multilevel logic networks derived from binary decision diagrams , 1991 .
[10] Bernd Becker,et al. Optimal-time multipliers and C-testability , 1990, SPAA '90.
[11] Paul Molitor,et al. Einführung in den VLSI-Entwurf , 1989, Leitfäden und Monographien der Informatik.
[12] Rolf Drechsler,et al. On the implementation of an efficient performance driven generator for conditional-sum-adders , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[13] C. C. Beh,et al. Do Stuck Fault Models Reflect Manufacturing Defects? , 1982, ITC.
[14] Luigi Cinque,et al. Parallel prefix computation on a pyramid computer , 1995, Pattern Recognit. Lett..
[15] D. C. King. Diagnosis and reliable design of digital systems , 1977 .
[16] Magdy S. Abadir,et al. Functional Testing of Semiconductor Random Access Memories , 1983, CSUR.
[17] Wojciech Maly,et al. Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.
[18] Bernd Becker. Efficient Testing of Optimal Time Adders , 1988, IEEE Trans. Computers.
[19] Bernd Becker,et al. Computations over finite monoids and their test complexity , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[20] Wilfried Daehn,et al. Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials , 1986, ITC.
[21] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[22] F. Frances Yao,et al. Computational Geometry , 1991, Handbook of Theoretical Computer Science, Volume A: Algorithms and Complexity.
[23] John Paul Shen,et al. The design of two easily-testable VLSI array multipliers , 1983, 1983 IEEE 6th Symposium on Computer Arithmetic (ARITH).
[24] Bernd Becker,et al. A uniform test approach for RCC-adders , 1991, Fundamenta Informaticae.
[25] Vojin G. Oklobdzija,et al. Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming , 1992, IEEE Trans. Computers.
[26] Bernd Becker,et al. A performance driven generator for efficient testable conditional-sum-adders , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[27] Silvio Turrini,et al. Optimal group distribution in carry-skip adders , 1989, Proceedings of 9th Symposium on Computer Arithmetic.
[28] S. Yang,et al. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .
[29] John Paul Shen,et al. Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[30] R. Stephenson. A and V , 1962, The British journal of ophthalmology.
[31] R. L. Wadsack,et al. Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.
[32] Jacob A. Abraham,et al. Generating Tests for Physical Failures in MOS Logic Circuits , 1983, ITC.
[33] Gordon L. Smith,et al. Model for Delay Faults Based upon Paths , 1985, ITC.
[34] Randall L. Geiger,et al. VLSI Design Techniques for Analog and Digital Circuits , 1989 .
[35] S. M. Reddy,et al. On the design of path delay fault testable combinational circuits , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.
[36] Yves Crouzet,et al. Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.
[37] Richard D. Eldred. Test routines based on symbolic logical statements , 1958, ACM '58.
[38] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[39] Belle W. Y. Wei,et al. Area-Time Optimal Adder Design , 1990, IEEE Trans. Computers.
[40] Bernd Becker,et al. On the Construction of Optimal Time Adders (Extended Abstract) , 1988, STACS.
[41] Sharad Malik,et al. A synthesis-based test generation and compaction algorithm for multifaults , 1991, 28th ACM/IEEE Design Automation Conference.