Reliable energy-aware application mapping and voltage-frequency island partitioning for GALS-based NoC

Reliable energy-aware application mapping, task scheduling, and voltage-frequency island partitioning so as to minimize the energy consumption while preserving the required bandwidth and latency is considered as a challenging problem in the designing of Multi-Processor System-on-Chip. To achieve modular design and low power consumption, Globally Asynchronous Locally Synchronous (GALS) design paradigm is a promising approach which fits very well with the voltage-frequency islands concept. In this paper, we formulate mapping problem of a real-time application with stochastic execution times onto multicore systems, scheduling tasks on processors, and assigning voltage-frequency levels to Processing Elements (PEs) as a Mixed Integer Linear Programming (MILP) in GALS-based Network-on-Chip. Furthermore, owing to the importance of reliability issue, we address the effects of transient faults in our proposed MILP formulation such that the reliability of the whole system incorporating several heterogeneous PEs is guaranteed to be better than a given threshold. Due to the NP-hardness of such a problem, a rounding by sampling-based heuristic algorithm is provided. Experimental results based on E3S benchmark suite and some real applications show the effectiveness of our proposed heuristic in achieving a near-optimal solution in a small fractional of time needed to find the optimal solution. Experimental results also show that, our formulation preserves the required reliability and increases the energy consumption by 70% in some cases.

[1]  Thomas D. Burd,et al.  The simulation and evaluation of dynamic voltage scaling algorithms , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[2]  J. F. Ziegler,et al.  Terrestrial cosmic ray intensities , 1998, IBM J. Res. Dev..

[3]  K. L. Shepard,et al.  Noise in deep submicron digital design , 1996, ICCAD 1996.

[4]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[5]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.

[6]  Chita R. Das,et al.  Design and analysis of an NoC architecture from performance, reliability and energy perspective , 2008 .

[7]  Yingtao Jiang,et al.  A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints , 2010, TACO.

[8]  Narayanan Vijaykrishnan,et al.  Reliability concerns in embedded system designs , 2006, Computer.

[9]  Luca Benini,et al.  Analysis of error recovery schemes for networks on chips , 2005, IEEE Design & Test of Computers.

[10]  Jian-Jia Chen,et al.  Optimistic Reliability Aware Energy Management for Real-Time Tasks with Probabilistic Execution Times , 2008, 2008 Real-Time Systems Symposium.

[11]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[12]  E. N. Elnozahy,et al.  Energy-Efficient Server Clusters , 2002, PACS.

[13]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[14]  Thomas D. Burd,et al.  Design issues for Dynamic Voltage Scaling , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[15]  David Z. Pan,et al.  Voltage and frequency island optimizations for many-core/networks-on-chip designs , 2010, The 2010 International Conference on Green Circuits and Systems.

[16]  Axel Jantsch,et al.  Networks on chip , 2003 .

[17]  Ragunathan Rajkumar,et al.  Critical power slope: understanding the runtime effects of frequency scaling , 2002, ICS '02.

[18]  Diana Marculescu,et al.  Speed and voltage selection for GALS systems based on voltage/frequency islands , 2005, ASP-DAC.

[19]  R. Hokinson,et al.  Historical trend in alpha-particle induced soft error rates of the Alpha/sup TM/ microprocessor , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[20]  Krishnan Srinivasan,et al.  A technique for low energy mapping and routing in network-on-chip architectures , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[21]  Krishnendu Chakrabarty,et al.  Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems , 2003, ICCAD 2003.

[22]  L. Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[23]  Narayanan Vijaykrishnan,et al.  A clock power model to evaluate impact of architectural and technology optimizations , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[24]  Arunabha Sen,et al.  Energy efficient mapping and voltage islanding for regular NoC under design constraints , 2010, Int. J. High Perform. Syst. Archit..

[25]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Radu Marculescu,et al.  Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[27]  Steven M. Nowick,et al.  A low-latency FIFO for mixed-clock systems , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

[28]  Soonhoi Ha,et al.  ILP based data parallel multi-task mapping/scheduling technique for MPSoC , 2008, 2008 International SoC Design Conference.

[29]  Rami Melhem,et al.  The effects of energy management on reliability in real-time embedded systems , 2004, ICCAD 2004.

[30]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Radu Marculescu,et al.  Contention-aware application mapping for Network-on-Chip communication architectures , 2008, 2008 IEEE International Conference on Computer Design.

[32]  Michael L. Scott,et al.  Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[33]  Rolf Ernst,et al.  Embedded program timing analysis based on path clustering and architecture classification , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[34]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[35]  Thomas D. Burd,et al.  Energy efficient CMOS microprocessor design , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[36]  Michael L. Scott,et al.  Hiding synchronization delays in a GALS processor microarchitecture , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[37]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[38]  Radu Marculescu,et al.  Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.

[39]  Kees G. W. Goossens,et al.  A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic , 2007, VLSI Design.

[40]  Rudy Lauwereins,et al.  Design, Automation, and Test in Europe , 2008 .

[41]  Radu Marculescu,et al.  Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[42]  Radu Marculescu,et al.  Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[43]  Mahmut T. Kandemir,et al.  Soft errors issues in low-power caches , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[44]  Krishnan Srinivasan,et al.  A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[45]  Emil Talpes,et al.  Variability and energy awareness: a microarchitecture-level perspective , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[46]  Alexander Hall,et al.  Energy efficient application mapping to NoC processing elements operating at multiple voltage levels , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[47]  David Z. Pan,et al.  A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[48]  Joel S. Emer,et al.  The soft error problem: an architectural perspective , 2005, 11th International Symposium on High-Performance Computer Architecture.

[49]  Petru Eles,et al.  Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[50]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.