Electrical test structures replicated in thin films of mono-crystalline silicon offer potential benefits as physical standards for linewidth and overlay metrology. When the test structure's features, the lattice of the monocrystalline film, and the surface plane of the film have particular mutual orientations, the junctions of the Kelvin voltage taps with the bridge feature of the test structure have three-dimensional geometries which can be specified by four well-defined dimensional parameters. Since the voltage-tap and bridge linewidths determine the magnitude of the voltage-tap-induced electrical bridge-length-shortening effect, measurement of the latter offers an additional means for validating measurements of the linewidth of the bridge feature. This paper reports the results of simulations of current-flow through voltage-tap-to-bridge junctions, thus providing values of the expected voltage-tap-induced electrical bridge-length-shortening effect for a particular application. In addition, the calculated values are compared with experimental measurements. A parametric representation of the effective voltage-tap-induced electrical bridge-length-shortening as a function of voltage-tap and bridge linewidths has been developed. Its purpose is to facilitate a rapid independent estimation of the values of the shortening effect generated during electrical linewidth and overlay measurements performed on test structures replicated in thin films of mono-crystalline silicon.