Concurrent Optimization of Low-Cost Regular Fabrics and Variation-Tolerant Circuit Techniques for Nanoscale SRAM

As CMOS scaling continues, manufacturing costs increase substantially in part due to the challenges of subwavelength lithography. Alternative manufacturing methods that are proposed to enable affordable scaling require extreme layout regularity. Since modern systems are embedding increasing amounts of memory, constructing SRAM circuits efficiently from extremely regular patterns is of utmost importance. Further, robust SRAM design is becoming more challenging due to high random variability in nanoscale processes. Low-cost layout fabrics and variation-tolerant SRAM circuit techniques must be jointly explored to determine the optimal design/manufacturing strategy for affordable scaling. This dissertation proposes a framework to systematically explore the fabric-circuit design space for the SRAM bitcell. The framework integrates performance models for various fabric-circuit solutions with an effective design space exploration strategy. Efficient statistical methods are used to accelerate SRAM parametric failure analysis. The design space of a given fabric-circuit solution, which is reduced due to extreme layout regularity, is exhaustively searched for pareto-optimal designs. The exhaustive exploration is accelerated via subsampling of the design space and highly parallelized design evaluations. The pareto-optimal fronts are used to compare various fabriccircuit solutions. As a demonstration, the framework is used to explore the bitcell design space in a 45nm SOI process. This study considers two low-cost regular fabrics, each with